The structure and functionality of non-volatile random access semiconductor memory devices has evolved in the last decade in order to match the specific needs and requirements of data storage and processing. Non-volatile memory devices are useful in many applications whenever data must be retained after devices are powered off. Upon restart of many computing or entertainment devices, initialization data must be available to enable a processor to load its programs and operating systems from peripheral storage such as hard disks or optical compact disks. Desirable features of non-volatile semiconductor memory devices include large capacity, high speed of writing, high speed of readout, repeated erasability, ease of writing and erasing of data as well as specific practical features that may allow for example reading or writing to specific sectors within the memory while protecting other sectors.
An early example of erasable non volatile memory is the Erasable Programmable Read Only Memory or EPROM. Such EPROM devices comprise a multiplicity of memory cells generally arranged in arrays of several thousand cells on the surface of a semiconductor chip, each cell comprising one or more metal oxide semiconductor (MOS) transistors. Each MOS transistor has a first control gate which consists of a metallic area separated from the drain or depletion area of the transistor by a thin oxide film and a second electrically insulated gate located between the control gate and the drain. Such cells retain the data in the form of stored electrical charge on the insulated gate. In order to erase an EPROM electrons generated by ultraviolet radiation from a special erase lamp are utilized. Such devices necessarily require the erasing of all sectors of the memory followed by a re-write of the new data to all sectors of the memory. The rewrite operation consists of injecting hot electrons into the floating gate. Such write-erase processes can be time consuming and subject to error generation especially if only small sections of the data stored need to be modified. An EPROM generally requires a high-voltage supply with substantial current-generating capability to generate the hot electrons. Furthermore, the process of generating hot electrons degrades the transistor gate regions, which limits the number of erase-write cycles that can be performed.
A more recent type of memory device, called EEPROM or electrically erasable PROM, utilizes electrons generated by the application of a high voltage difference between a control gate located above the insulated gate and the drain region of the MOS transistor, to pump charge into or out of the insulated gate. An EEPROM is distinguished from an EPROM by two features:
1) the program and erase operations can be accomplished on a byte-by-byte basis, whereas, in an EPROM, the erase operation is global and only the program operation is byte-by-byte; and PA1 2) the mechanism underlying the program and erase operations in an EEPROM is Fowler-Nordheim (FN) tunneling, whereas, in an EPROM, it is hot-electron injection for programming (typically a high-current mechanism), and UV-erase for the erase operation. PA1 (1) selected GWL, selected BXAj=&gt;WL=-8 V PA1 (2) selected GWL, deselected BXAj=&gt;WL=0 V PA1 (3) deselected GWL, selected BXAj=&gt;+.vertline.VtP1.vertline.&gt;WL&gt;-.vertline.VtN1.vertline. PA1 (4) deselected GWL, deselected BXAJ=&gt;+.vertline.VtP1.vertline.&gt;WL&gt;-.vertline.VtN1.vertline.. PA1 (1) the VPN is -11 V, the SPV is 3 V and the SNV is between 0 V and -0.5 V; PA1 (2) the VPN is -11 V, the SPV is between 0.5 V and 3 V, and the SNV is between 0 V and -0.5 V; or PA1 (3) the VPN is between -6 V and -15 V, the SPV is between 0.5 and 3 V, and the SNV is between 0 V and -0.5 V.
Flash EPROMs, which have become the standard non-volatile memory are hybrid devices, share features of the EPROM and EEPROMS. That is, similarly to EPROMS, flash memories have a global (or sector, in more recent types) erase mode. Similarly to EEPROMS, flash memories can be erased and programmed electrically. The characteristics of the different types of non-volatile memory are summarized in Table 1. The present invention is implemented in a flash EPROM with tunneling program and sector tunneling erase. The basic operation of a Fowler-Nordheim flash EPROM is now described in reference to FIG. 1.
TABLE 1 ______________________________________ Memory Type Program Mechanism Erase Mechanism ______________________________________ EPROM hot-electron (high current) global (non-byte) UV EEPROM FN-tunneling (low V) FN-tunneling (byte operation) electrical Flash hot-electron or tunneling FN-tunneling global or semi- EPROM injection global (non-byte operating) electrical ______________________________________
Referring to FIG. 1, there is shown a block diagram of a flash memory 110. This block diagram is also representative of the architecture of other types of memories. The flash memory 110 includes a memory array 112, an address decoder 114, a control circuit 116, an input/output (I/O) data circuit 118 and a column I/O circuitry 120. The memory 110 operates in response to external signals provided by a controlling device 122, such as a microprocessor.
The principle of operation of flash memories, such as the memory 110, is well known and therefore is only briefly described herein. The controller 122 initiates a memory operation by asserting a chip enable signal 101 and supplying address signals A0-AN (corresponding to 2N+1 memory locations) designating the address of a memory location where the operation is to be performed. If the memory operation is a write operation, the controller 122 supplies the data to be written to the addressed memory location via the bi-directional input output lines l/O0-I/Ok (corresponding to k+1 bit memory words). If the memory operation is a read operation, the stored information from the addressed location is read out from the same bi-directional input output lines I/O0-I/Ok. The memory 110 also provides connections for external power supply (Vcc) and ground (GND) signals.
The heart of the memory 110 is the memory array 112, which consists of flash memory cells, each capable of storing one bit of data, arranged in rows and columns. In the conventional manner, all of the cells in one row are energized for a memory operation (either a read or a write) by a word line WL uniquely associated with that row. A memory operation cannot be performed unless the word line associated with the target row of cells is activated.
At least a subset of the cells in a row (typically all of the cells that store data for one memory word) can be accessed simultaneously for a given memory operation via the bit lines BL. When the memory operation is a read, the bit lines BL are coupled to sense amplifiers in the column I/O 120 that "sense" the data stored in the corresponding cells of the row whose word line WL is active. When the memory operation is a write operation the bit lines BL carry the signals used to program the corresponding cells of the row associated with the active word line.
The control circuitry 116 controls the other blocks of the memory 110 in accordance with the chip enables 101. Depending on the operation to be performed, the control circuitry issues the appropriate control signals 117a, 117b to the decoder 114 and the I/O data circuit, respectively.
Regardless of whether the memory operation is a write or a read, the decoder 114 decodes the address signals A0-AN and activates the word line WL of the row that includes the memory word that is the target of the current memory operation. If the operation is a write, the I/O data circuitry 118 buffers the input data signals I/O0-I/Ok and outputs the buffered data to the column I/O 120 via the bi-directional data bus 119. The column I/O 120 then latches the input signals in parallel onto the corresponding bit lines BL0-BLK. The signals on the bit lines BL0-BLK are used to program the cells composing the word whose word line was activated for the current operation by the decoder 114.
If the operation is a read, sense amplifiers in the column I/O 120 sense the signals on the respective bit lines BL, convert the sensed signals into binary (e.g., high or low) voltages that represent the programmed state of the addressed word and output the word's bit values to the I/O data circuit via the bi-directional bus 119. The output data are buffered by the I/O data circuit 118 and latched onto the bi-directional data lines I/O0-I/Ok for use by the controller 122.
Referring to FIG. 2, there is shown a prior art implementation of a decoder 202 used with a flash memory array 204. The decoder 202 includes global decoders 206 and local decoders 208; is responsive to global and local address signals AXA0-19, BXA0-3 and positive and negative power supply signals VPP1, VBB1; and drives the word lines WL associated with the array 204. This decoder implements a common two-level decoding scheme where the global decoders 206 decode the global address bits AXA0-19 and the local decoders 208 decode the local address bits BXA0-3 (i.e., the total address space is 24 bits). The set of local word lines associated with a single global word line composes a sector. Because the array 204 employs flash cells, the decoder 202 must generate different voltage levels on selected and de-selected word lines WL depending on the mode of operation (i.e., erase, program or read modes). The operating voltage conditions for these signals for the different modes are shown in Table 2.
TABLE 2 ______________________________________ VPP1 VBB1 AXA0-19 BXA0-3 ______________________________________ Erase 10 V 0 V 10 V/0 V 10 V Program 0 V -8 V -8 V/0 V -8 V/0 V Read 3 V 0 V 3 V/0 V 3 V/0 V ______________________________________
Except for the erase mode, two voltage levels are typically shown in Table 2 for the AXA0-19 and BXA0-3 signals, corresponding to voltage levels representing selected and unselected address bits. For the erase mode, only one signal level (10 V) is shown for the BXA0-3 signals. This is due to the fact that the flash memory including the decoder 202 employs a sector-erase strategy, where all cells associated with a single global word line are erased simultaneously.
When a global decoder 206-i decodes its preset address from the address signals AXA0-19, it generates a low signal (i.e., a signal at the VBB1 level) on its inverted global word line /GLi and a high signal (i.e., a signal at the VPP1 level) on its corresponding non-inverted global word line GLi, which is generated from the /GLi signal with an inverter 210. Otherwise, the global decoder 206i generates high and low signals on the global word lines /GLi and GLi, respectively. Each global word line is coupled to a group of local decoders/word line drivers 208, each of which controls a respective local word line WLj. Each local decoder 208j drives its local word line WLj to either the VPP1 or VBB1 voltage level as a function of the voltage levels of the associated global word line GLi; the voltage supplies VPP1, VBB1; and the address signals BXA0-3.
Referring to Table 2, in erase, program and read modes, the local decoder 208 drives selected word lines WL to 10 V, -8 V and 3 V respectively, where selected word lines are those word lines associated with a selected global word line and a set of selected BXA0-3 address bits. The local decoder 208 passes these different voltage levels using two n-channel transistors N1, N2 and a p-channel transistor P1 connected as shown in FIG. 2. The operation of the local decoder 208 is now described for erase and program modes.
In erase mode, the word line WL voltage level depends only on the state of the global word lines. Selected global word lines /GLi, GLi are at 0 V and 10 V. In each locai decoder 208j coupled to a selected global word line the transistors P1 and N2 couple the high voltage (10 V) on a corresponding one of the address lines BXAj to a respective word line WLj. This causes the entire sector to be erased (i.e., all of cells in that sector will have a high threshold Vt following the erase operation). Unselected global word lines /GLi, GLi are at 10 V and 0 V. The transistor N1 in each of the local drivers 208 coupled to a deselected global word line pulls its local word line WL down to 0 V, ensuring that the associated row of cells is not erased.
In program mode, there are four combinations of selected global word lines and address bits BXA0-3 that determine the word line WL voltage levels as follows:
In program mode, selected global word lines /GLi, GLi are at -8 V and 0 V. In a local driver 208j coupled to a selected address bit BXAJ at -8 V, the transistors P1 and N2 each couple the low voltage (-8 V) on the selected address line BXAJ to the selected local word line WLj. This causes the row of cells coupled to the word line WLj and the selected address lines BXAj to be programmed (i.e., all of the selected cells in that row will have a low threshold Vt after the programming operation). In each of the unselected local drivers 208k (where k is different from j) associated with the selected global word line, the transistors P1 and N2 couple their word lines WLk to 0 V.
In program mode, unselected global word lines /GLi, GLi are at 0 V and -8 V. In a local driver 208j coupled to a selected address bit BXAJ at -8 V, the transistor N1 couples the local word line WLj to +.vertline.VtP1.vertline.&gt;WL&gt;-.vertline.VtN1.vertline.. In a local driver 208k coupled to an unselected address BXAk at 0 V, the transistors P1 and N1 combine to set the word line WLj voltage level to: +.vertline.VtP1.vertline.&gt;WL&gt;-.vertline.VtN1.vertline..
Thus, for selected global word lines GWL, the voltage level of the associated selected and unselected local word lines WL is well-controlled. However, for unselected global word lines, the local word line WL voltage levels are unstable for both selected and unselected local word lines. Due to these variations in word line levels, memory cells coupled to unselected global word lines GWL could be disturbed during program operations if the threshold voltage Vt of the transistor N1 is sufficiently large.